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FEATURES 16-Bit Resolution AD5543 14-Bit Resolution AD5553 1 LSB DNL 2 LSB INL for AD5543 1 LSB INL for AD5553 Low Noise 12 nV/Hz Low Power, IDD = 10 A 0.5 s Settling Time 4Q Multiplying Reference-Input 2 mA Full-Scale Current 20%, with VREF = 10 V Built-in RFB Facilitates Voltage Conversion 3-Wire Interface Ultracompact MSOP-8 and SOIC-8 Packages APPLICATIONS Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs GENERAL DESCRIPTION
Current Output/ Serial Input, 16-/14-Bit DAC AD5543/AD5553
FUNCTIONAL BLOCK DIAGRAM
AD5543/AD5553
VDD D/A CONVERTER 16 OR 14 CS CONTROL LOGIC DAC REGISTER 16 OR 14 CLK SDI 16-/14-BIT SHIFT REGISTER GND IOUT RFB
VREF
1.0 0.8 0.6 0.4
The AD5543/AD5553 are precision 16-/14-bit, low power, current output, small form factor digital-to-analog converters. They are designed to operate from a single 5 V supply with a 10 V multiplying reference. The applied external reference VREF determines the full-scale output current. An internal feedback resistor (RFB) facilitates the R-2R and temperature tracking for voltage conversion when combined with an external op amp. A serial-data interface offers high speed, 3-wire microcontroller compatible inputs using serial data in (SDI), clock (CLK), and chip select (CS). The AD5543/AD5553 are packaged in ultracompact (3 mm 4.7 mm) MSOP-8 and SOIC-8 packages.
INL - LSB
0.2 0 -0.2 -0.4 -0.6 -0.8
0
12288
16384
20480
24575
28672
32768
36864
40960
45056
49152
53248
57344
61440
CODE
Figure 1. Integral Nonlinearity Error
REF LEVEL 0.000dB /DIV 12.000dB MARKER 4 311 677.200Hz MAG (A/R) -2.939dB
FFFFH 8000H 4000H 2000H 1000H 0800H 0400H 0200H 0100H 0080H 0040H 0020H 0010H 0008H 0004H 0002H 0001H 0000H
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
10 100 START 10.000Hz
1k
10k
100k 1M 10M STOP 50 000 000.000Hz
Figure 2. Reference Multiplying Bandwidth
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
65536
4096
8152
-1.0
AD5543/AD5553-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter STATIC PERFORMANCE1 Resolution Relative Accuracy Differential Nonlinearity Output Leakage Current Full-Scale Gain Error Full-Scale Tempco2 REFERENCE INPUT VREF Range Input Resistance Input Capacitance2 ANALOG OUTPUT Output Current Output Capacitance2 LOGIC INPUTS AND OUTPUT Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance2 INTERFACE TIMING 2, 4 Clock Input Frequency Clock Width High Clock Width Low CS to Clock Setup Clock to CS Hold Data Setup Data Hold SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity AC CHARACTERISTICS4 Output Voltage Settling Time Symbol N INL DNL IOUT GFSE TCVFS VREF RREF CREF IOUT COUT VIL VIH IIL CIL fCLK tCH tCL tCSS tCSH tDS tDH VDD RANGE IDD Logic Inputs = 0 V Logic Inputs = 0 V PDISS PSS VDD = 5% tS BW Q VOUT/VREF Q THD eN To 0.1% of Full Scale, Data = 0000H to FFFFH to 0000H for AD5543 Data = 0000H to 3FFFH to 0000H for AD5553 VREF = 5 V p-p, Data = FFFFH VREF = 0 V, Data = 7FFFH to 8000H for AD5543 Data = 1FFFH to 2000H for AD5553 Data = 0000H, VREF = 100 mV rms, same channel CS = 1, and fCLK = 1 MHz VREF = 5 V p-p, Data = FFFFH, f = 1 kHz f = 1 kHz, BW = 1 Hz Data = FFFFH for AD5543 Data = 3FFFH for AD5553 Code Dependent
(@ VDD = 5 V 10%, VSS = 0 V, IOUT = Virtual GND, GND = 0 V, VREF = 10 V, TA = Full operating temperature range, unless otherwise noted.)
Condition 1 LSB = VREF/216 = 153 V when VREF = 10 V AD5543 1 LSB = VREF/214 = 610 V when VREF = 10 V AD5553 Grade: AD5553C Grade: AD5543B Monotonic Data = 0000H, TA = 25C Data = 0000H, TA = TA max Data = FFFFH 5V 16 14 1 2 1 10 20 1/ 4 1 -15/+15 5 5 2 200 0.8 2.4 10 10 50 10 10 0 10 5 10 4.5/5.5 10 0.055 0.006 0.5 10% Unit Bits Bits LSB max LSB max LSB max nA max nA max mV typ/max ppm/C typ V min/max k typ3 pF typ mA typ pF typ V max V min A max pF max MHz ns min ns min ns min ns min ns min ns min V min/max A max mW max %/% max s typ MHz typ nV-s typ dB nV-s typ dB typ nV/Hz
Reference Multiplying BW DAC Glitch Impulse Feedthrough Error Digital Feedthrough Total Harmonic Distortion Output Spot Noise Voltage
4 7 -65 7 -85 12
NOTES 1 All static performance tests (except I OUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 R FB terminal is tied to the amplifier output. The op amp +IN is grounded and the DAC I OUT is tied to the op amp -IN. Typical values represent average readings measured at 25 C. 2 These parameters are guaranteed by design and are not subject to production testing. 3 All ac characteristic tests are performed in a closed-loop system using an AD841 I-to-V converter amplifier. 4 All input control signals are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
-2-
REV. A
AD5543/AD5553
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +8 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 V, +18 V Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . -0.3 V, +8 V V(IOUT) to GND . . . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V Input Current to Any Pin except Supplies . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . (TJ Max - TA )/ JA Thermal Resistance JA 8-Lead Surface Mount (MSOP-8) . . . . . . . . . . . . . 150C/W 8-Lead Surface Mount (SOIC-8) . . . . . . . . . . . . . . 100C/W Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150C Operating Temperature Range Models B, C . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature RN-8, RM-8 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . 215C RN-8, RM-8 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin No. Mnemonic Function 1 2 CLK SDI Clock Input. Positive-edge triggered, clocks data into shift register. Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored. Internal Matching Feedback Resistor. Connects to external op amp for voltage output. DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance versus code. DAC Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. Analog and Digital Ground Positive Power Supply Input. Specified range of operation 5 V 10%. Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge. See Truth Table for operation.
3 4
RFB VREF
5
IOUT
6 7 8
GND VDD CS
PIN CONFIGURATION MSOP and SOIC-8
CLK 1 SDI 2
VDD TOP VIEW RFB 3 (Not to Scale) 6 GND
7
AD5543/ AD5553
8
CS
VREF 4
5
IOUT
ORDERING GUIDE*
Model AD5543BR AD5543BRM AD5553CRM
INL (LSB) 2 2 1
RES (LSB) 16 16 14
Temperature Range
Package Description
Package Option RN-8 RM-8 RM-8
Marking AD5543 DXB DUC
-40C to +85C SOIC-8 -40C to +85C MSOP-8 -40C to +85C MSOP-8
*The AD5543 contains 1040 transistors. The die size measures 55 mil
73 mil, 4,015 sq. mil.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5543/AD5553 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
-3-
AD5543/AD5553-Typical Performance Characteristics
1.0 0.8 0.6 0.4
1.0 0.8 0.6 0.4
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE - Decimal
DNL - LSB
INL - LSB
0.2
0.2 0
-0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 CODE - Decimal 12288 14336 16384
TPC 1. AD5543 Integral Nonlinearity Error
TPC 4. AD5553 Differential Nonlinearity Error
1.0 0.8 0.6 0.4 DNL - LSB 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE - Decimal
1.5 VREF = 2.5V TA = 25 C 1.0
LINEARITY ERROR - LSB
0.5 INL 0 DNL -0.5
-1.0
GE
-1.5
2
4
6 SUPPLY VOLTAGE VDD - V
8
10
TPC 2. AD5543 Differential Nonlinearity Error
TPC 5. Linearity Errors vs. VDD
1.0 0.8 0.6 0.4 INL - LSB 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2048 4096 6144 8192 10240 CODE - Decimal 12288 14336 16384
5 VDD = 5V TA = 25 C
SUPPLY CURRENT IDD - mA
4
3
2
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LOGIC INPUT VOLTAGE VIH - V
TPC 3. AD5553 Integral Nonlinearity Error
TPC 6. Supply Current vs. Logic Input Voltage
-4-
REV. A
AD5543/AD5553
3.0 2.5
SUPPLY CURRENT - mA
2.0 5555H 1.5 8000H 1.0 FFFFH 0000H 0.5
0 10k
100k
1M 10M CLOCK FREQUENCY - Hz
100M
TPC 7. AD5543 Supply Current vs. Clock Frequency
TPC 10. Settling Time
90 80 70 60
PSRR - dB
VDD = 5V 10% VREF = 10V
CS (5V/DIV) VDD = 5V VREF = 10V CODES 8000H 7FFFH
50 40 30 20 10 0 10
VOUT (50mV/DIV)
100
10k 1k FREQUENCY - Hz
100k
1M
0
0.5
1.0
1.5
2.0 2.5 3.0 TIME - s
3.5
4.0
4.5
5.0
TPC 8. Power Supply Rejection vs. Frequency
TPC 11. Midscale Transition and Digital Feedthrough
REF LEVEL 0.000dB FFFFH 8000H 4000H 2000H 1000H 0800H 0400H 0200H 0100H 0080H 0040H 0020H 0010H 0008H 0004H 0002H 0001H 0000H
/DIV 12.000dB
MARKER 4 311 677.200Hz MAG (A/R) -2.939dB
10 100 START 10.000Hz
1k
10k
100k 1M 10M STOP 50 000 000.000Hz
TPC 9. Reference Multiplying Bandwidth
REV. A
-5-
AD5543/AD5553
SDI D15 D14 D13 D12 D11 D10 D9 D8 D1 D0
CLK
tDS tCSS
t
DH
tCH
tCL
tCSH
CS
Figure 3a. AD5543 Timing Diagram
SDI
D13
D12
D11
D10
D9
D8
D7
D6
D1
D0
CLK
tDS tCSS
t
DH
tCH
tCL
tCSH
CS
Figure 3b. AD5553 Timing Diagram
Table I. Control-Logic Truth Table
CLK X + X X
CS H L H +
Serial Shift Register Function No Effect Shift Register Data Advanced One Bit No Effect Shift Register Data Transferred to DAC Register
DAC Register Latched Latched Latched New Data Loaded from Serial Register
+ positive logic transition; X Don't Care
Table II. AD5543 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB Bit Position Data-Word B15 D15 B14 D14 B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2
LSB B1 D1 B0 D0
Table III. AD5553 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB Bit Position Data-Word* B13 D13 B12 D12 B11 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2
LSB B1 D1 B0 D0
*A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered will be transferred to the DAC register when CS returns to logic high.
-6-
REV. A
AD5543/AD5553
CIRCUIT OPERATION
The AD5543/AD5553 contains a 16-/14-bit, current output, digital-to-analog converter, a serial input register, and a DAC register. Both converters use a 3-wire serial data interface.
D/A Converter Section
The DAC architecture uses a current steering R-2R ladder design. Figure 4 shows the typical equivalent DAC structure. The DAC contains a matching feedback resistor for use with an external op amp, (see Figure 5). With RFB and IOUT terminals connected to the op amp output and inverting node respectively, a precision voltage output can be achieved as: VOUT = - VREF x D / 65, 536 ( AD 5543) VOUT = - VREF x D / 16, 384 ( AD 5553) Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal logic to drive the DAC switches' ON and OFF states.
VDD R VREF 2R 2R 2R R S2 5k S1 IOUT GND R R RFB
various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the AD5543 on the amplifier's inverting input node. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. To maintain good analog performance, power supply bypassing of 0.01 F to 0.1 F ceramic or chip capacitors in parallel with a 1 F tantalum capacitor is recommended. Due to degradation of power supply rejection ratio in frequency, users must avoid using switching power supplies.
SERIAL DATA INTERFACE
(1) (2)
The AD5543/AD5553 uses a 3-wire (CS, SDI, CLK) serial data interface. New serial data is clocked into the serial input register in a 16-bit data-word format for AD5543. The MSB is loaded first. Table II defines the 16 data-word bits. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK, subject to the data setup and hold time requirements specified in the interface timing specifications. Only the last 16 bits clocked into the serial register are interrogated when the CS pin is strobed to transfer the serial register data to the DAC register. Since most microcontrollers output serial data in 8-bit bytes, two data bytes can be written to the AD5543/AD5553. After loading the serial register, the rising edge of CS transfers the serial register data to the DAC register; during this strobe, the CLK should not be toggled. For the AD5553, with 16-bit clock cycles, the two LSBs are ignored.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zener diodes connected to ground (GND) and VDD as shown in Figure 6.
VDD DIGITAL INPUTS 5k
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY; SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED
Figure 4. Equivalent R-2R DAC Circuit
Note that a matching switch is used in series with the internal 5 k feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity.
VDD U1 VDD VREF VREF GND RFB IOUT V+ AD8628 V- U2 VO
DGND
Figure 6. Equivalent ESD Protection Circuits
PCB Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead length PCB layout design. The leads to the input should be as short as possible to minimize IR drop and stray inductance. It is also essential to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 F to 0.1 F disc or chip ceramic capacitors. Low-ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple The PCB metal traces between VREF and RFB should also be matched to minimize gain error.
AD5543/AD5553
-5V
Figure 5. Voltage Output Configuration
These DACs are also designed to accommodate ac reference input signals. The AD5543 accommodates input reference voltages in the range of -12 V to +12 V. The reference voltage inputs exhibit a constant nominal input resistance value of 5 k, 30%. The DAC output (IOUT) is code-dependent, producing
REV. A
-7-
AD5543/AD5553
APPLICATIONS Stability
VDD U1 VDD VREF VREF GND RFB IOUT AD8628 C1
Bipolar Output
The AD5543/AD5553 is inherently a 2-quadrant multiplying D/A converter. That is, it can easily be set up for unipolar output operation. The full-scale output polarity is the inverse of the reference input voltage. In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished by using an additional external amplifier U4 configured as a summing amplifier (see Figure 9). In this circuit, the second amplifier U4 provides a gain of 2 that increases the output span magnitude to 5 V. Biasing the external amplifier with a 2.5 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -2.5 V) to midscale (VOUT = 0 V) to full-scale (VOUT = +2.5 V). VOUT = (D / 32, 768 - 1) x VREF ( AD 5543) VOUT = (D / 16, 384 - 1) x VREF ( AD 5553) For AD5543, the resistance tolerance becomes the dominant error of which users should be aware.
R1 10k R2 0.01% C2 U4 +5V ADR03 VOUT VIN GND U3 U1 VDD VREF GND 5k C1 IOUT 1/2AD8620 0.01% R3 RFB V+ 1/2AD8620 V- -5V -2.5 < VO < +2.5 VO +5V
VO
AD5543/AD5553
U2
Figure 7. Optional Compensation Capacitor for Gain Peaking Prevention
In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible, and proper PCB layout technique must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. An optional compensation capacitor C1 can be added for stability as shown in Figure 7. C1 should be found empirically but 20 pF is generally adequate for the compensation.
Positive Voltage Output
(3) (4)
0.01% 10k
To achieve the positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor's tolerance errors. To generate a negative reference, the reference can be level-shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and -2.5 V respectively, (see Figure 8).
+5V ADR03 VOUT VIN +5V GND V+ 1/2AD8620 V- -5V U3 -2.5V GND U1 VDD VREF RFB C1 IOUT 1/2AD8628 VO
+5V
AD5553 ONLY
U2
Figure 9. Four-Quadrant Multiplying Application Circuit
U4
AD5543/AD5553
U2
0 < VO < +2.5
Figure 8. Positive Voltage Output Configuration
-8-
REV. A
AD5543/AD5553
Programmable Current Source
Figure 10 shows a versatile V-I conversion circuit using an improved Howland Current Pump. In addition to the precision current conversion it provides, this circuit enables a bidirectional current flow and high voltage compliance. This circuit can be used in 4 to 20 mA current transmitters with up to 500 of load. In Figure 10, it can be shown that if the resistor network is matched, the load current is: IL =
If the resistors are perfectly matched, ZO is infinite, which is desirable, and behaves as an ideal current source. On the other hand, if they are not matched, ZO can be either positive or negative. Negative can cause oscillation. As a result, C1 is needed to prevent the oscillation. For critical applications, C1 could be found empirically, but typically falls in the range of few pF.
VDD U1
R3 R3 in theory can be made small to achieve the current needed within the U3 output current driving capability. This circuit is versatile such that AD8510 can deliver 20 mA in both directions and the voltage compliance approaches 15 V, which is limited mainly by the supply voltages of U3. However, users must pay attention to the compensation. Without C1, it can be shown that the output impedance becomes: R1' R3( R1 + R2) ZO = (6) R1 R2' + R3' - R1' R2 + R3
(R2 + R3) / R1 x V
REF
xD
(5)
VREF
VDD VREF GND
RFB IOUT AD8628 C1 10pF R1' 150k R2' 15k
AD5543/AD5553
U2 VDD V+ AD8510 V- VSS VL R1 150k R2 15k LOAD IL U3 R3' 50
(
)
(
)
R3 50
Figure 10. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance Capabilities
REV. A
-9-
AD5543/AD5553
OUTLINE DIMENSIONS 8-Lead microSOIC Package [MSOP] (RM-8)
Dimensions shown in millimeters
3.00 BSC
8
5
3.00 BSC
1 4
4.90 BSC
PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.40
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075)
0.50 (0.0196) 0.25 (0.0099)
45
0.51 (0.0201) 0.33 (0.0130)
1.27 (0.0500) 0.41 (0.0160)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-10-
REV. A
AD5543/AD5553 Revision History
Location 2/03--Data Sheet changed from REV. 0 to REV. A. Page
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. A
-11-
-12-
C02917-0-2/03(A)
PRINTED IN U.S.A.

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